Cadence SPB 16.6(Full Software)

OrCAD is a proprietary software tool suite used primarily for electronic design automation (EDA). The software is used mainly by electronic design engineers and electronic technicians to create electronic schematics and electronic prints for manufacturing printed circuit boards.
The name OrCAD is a portmanteau, reflecting the company and its software's origins: Oregon + CAD.

OrCAD is a suite of products for EDA, and includes a schematic editor (Capture), a circuit simulator (PSpice) and a PCB designer.

OrCAD Capture

OrCAD Capture is a schematic capture application, and part of the OrCAD circuit design suite.[14]
Unlike NI Multisim, Capture does not contain in-built simulation features, but exports netlist data to the simulator, OrCAD EE. Capture can also export a hardware description of the circuit schematic to Verilog or VHDL, and netlists to circuit board designers such as OrCAD Layout, Allegro, and others.[15]
Capture includes a component information system (CIS), that links component package footprint data or simulation behavior data, with the circuit symbol in the schematic.[15]
Capture includes a TCL/TK scripting functionality that allows users to write scripts, that allow customization and automation. Any task performed via the GUI may be automated by scripts.[15]
The OrCAD Capture Marketplace enables customers to share and sell add-ons and design resources. Such add-ons can customize the design environment and add features and capabilities.[15]
Capture can interface with any database which complies with Microsoft's ODBC standard etc. Data in an MRP, ERP, or PDM system can be directly accessed for use during component decision-making process.

OrCAD EE PSpice

OrCAD EE PSpice is a SPICE circuit simulator application for simulation and verification of analog and mixed-signal circuits.[16] PSpice is an acronym for Personal Simulation Program with Integrated Circuit Emphasis.
OrCAD EE typically runs simulations for circuits defined in OrCAD Capture, and can optionally integrate with MATLAB/Simulink, using the Simulink to PSpice Interface (SLPS).[17] OrCAD Capture and PSpice Designer[18] together provide a complete circuit simuation and verification solution with schematic entry, native analog, mixed signal, and analysis engines.
PSpice was a modified version of the academically developed SPICE, and was commercialized by MicroSim in 1984. MicroSim was purchased by OrCAD a decade later in 1998.
OrCAD PSpice Designer is available in two options- PSpice Designer and PSpice Designer Plus.
OrCAD PSpice Designer includes OrCAD Capture and OrCAD PSpice solution. An upgrade option to PSpice Designer Plus provides the PSpice Advanced Analysis[19] simulation engine for functional simulation and improvement in design yield and reliability.
The PSpice Advanced Analysis simulation capabilities covers various analyses- Sensitivity, Monte Carlo, Smoke (Stress), Optimizer, and Parametric Plotter providing in depth understanding of circuit performance beyond basic validation.
The OrCAD PSpice Simulink- PSpice Integration(SLPS)[20] provides co-simulation and helps verify system level behavior.
A circuit to be analyzed using PSpice is described by a circuit description file, which is processed by PSpice and executed as a simulation. PSpice creates an output file to store the simulation results, and such results are also graphically displayed within the OrCAD EE interface.
OrCAD EE is an upgraded version of the PSpice simulator, and includes automatic circuit optimization and support for waveform recording, viewing, analysis, curve-fitting, and post-processing.[16][21] OrCAD EE contains an extensive library of models for physical components, including around 33,000 analog and mixed-signal devices and mathematical functions.[16] OrCAD EE also includes a model editor, support for parameterized models, auto-convergence and checkpoint restart, several internal solvers and a magnetic part editor.


The SPB 16.6 Release is available! You can download it from the Cadence Software downloads site.
Here are just a few press announcements on the 16.6 release –
1. New Allegro 16.6 Release Accelerates Timing Closure on High-Speed PCB Interfaces by 30 to 50 Percent
2. Announcing OrCAD 16.6—A One-Two Punch for Mainstream PCB Engineers
3. Cadence Allegro Accelerates Product Creation Through Efficient Collaborative ECAD Environment Using Microsoft SharePoint
4. Allegro 16.6: Easing PCB Design for Multi-Gigabit/Second Signals

What’s New in Cadence OrCAD 16.6 Release ?
Cadence Releases OrCAD 16.6, Boosts PSpice Performance By Up to 20 Percent

Allegro PCB Editor

  Support for embedding components with dual-sided contacts and vertical components on the inner layers of a PCB
  New embedded cavity DRCs
  Faster timing closure with auto-interactive route delay tuning (AiDT)
  PCB Team Design Option accelerates design implementation
  Auto-interactive pin-swap (“Planning Mode”) for FPGAs within Allegro PCB Editor using Allegro FPGA System Planner under-the-hood
  Offset routing allows users to route off-orthogonal angles to avoid coupling high-speed signals with substrate glass fiber-weaves
  New Slide function
  Export / Import design data to and from manufacturing using the open industry-standard IPC-2581
  New artwork control form allows users to assign film record classes and subclasses to a film record
  General Edit Application Mode allows users to assign a single region constraint to multiple region shapes
  Align components by edge (top, center, bottom) using DFA constraints or equal spacing (controllable by user-defined equal spacing and + and - buttons)
  Support for text in Place Replicate
  Quickplace allows component overlap (user-defined % overlap) to get the components on the board faster
  Refresh a symbol by instance
  New command allows users to add rectangles with parameterized corners (champhered, rounded, or orthogonal)
  Dynamic shape allows thermal width for cross-hatch shapes based on the cross-hatch line width
  New display option overlays net names along cline path, pins, shapes, and flow lines
  Lines and text can now be moved outside their present class-subclass structure
  Select objects by “Lasso” or “path”
  Highlight or de-highlight nets associated with a component
  DRC can now be run “by window” when online DRC is turned off
  Specify any text for the associative dimension value using the optional Text filed in the Options tab
  Specify separate output files for plated versus non-plated (NC) routing
  Pastemask-to-pastemask DRC will check the “Package Geometry - Pastemask_Top” shapes within the same symbol
  and more …

Allegro Package Designer

  Shape Shorting - Via Array
  Bondwire Text In
  Wirebond Application Mode
  Assembly Design Rule Check (ADRC)
  Open Cavities
  Geometry to Symbol
  and more …

Allegro PCB SI

  Setup/Audit Enhancements
  SigXP Via Enhancements
  Auto-solving Models in SigXP
  Channel Analysis Enhancements
  PDN Enhancements
  PDN DeCap Management
  and more …

Allegro RF SiP

  Library Manager Flow Improvements
  Support for curves in RF Shape Routing
  Bond Wire Retain Flow
  and more …

Allegro RF PCB

  Improvements to importing from Agilent ADS to Allegro Design Authoring
  Support for new ADS RF etch elements libraries
  Snap improvements
  “Add Connect” allows users to connect to the edge of a pad, or overlapping a pad
  Scaled copy allows snap to pad edge
  Unnecessary DRC errors removed when netlist is imported into Allegro PCB Editor
  Via exchange between ADS and Allegro environment
  and more …

Allegro Design Entry HDL

  Interface Aware Design (Netgroups)
  Split hierarchical symbols and support for hierarchical nets in the Cross Referencer enable team design on designs with large pin-count components like microprocessors
  Constraint comparison utility allows users to compare constraints from two HDL schematics, PCB designs (brd), modules, and constraint files (dcf)
  Enhanced object filtering and visibility in the Constraint Manager, plus an option to use higher level net names for Xnet naming
  and more …

Allegro FPGA System Planner

  Support for additional FPGA architectures from Actel (ProASIC3), Altera (Cyclone V, Stratix V), and Xilinx (Virtex 7)
  Auto-interactive pin-swap (“Planning Mode”) for FPGAs within Allegro PCB Editor using Allegro FPGA System Planner under-the-hood
  Support for new termination schemes
  Design Compare
  and more …

Allegro Design Workbench

  Team Design Authoring solution now provides work-in-progress design data management and an efficient collaboration environment using SharePoint 2010
  Comprehensive library model management for logical schematic blocks and physical modules
  Configuration Manager Enhancements
  Design Migration Enhancements
  Flow Manager Enhancements
  and more …

Allegro Design Entry CIS

  OrCAD Schematic – Signal Integrity Flow
  Enhanced Save Function for Design and Library
  Enhancements in the Find Function
  Enhancements in Cache Updates
  Project Save As Enhancements
  NetGroup Enhancements
  Design Level Auto-RefDes
  Locking Reference and Designator Properties
  Design Rule Check (DRC) Enhancements
  Full RefDes support
  CIS – Link Database Part
  and more …

Allegro AMS Simulator

  Advanced Options
  Probe DAT Version Upgrade - 64-Bit Data Precision
  Undo Support for Capture Netlists
  Enhanced IBIS Support
  Multi-Core Engine Support
  Configuring Menus and Toolbars
  Encryption Enhancements
  New Models
  and more …


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