[ FreeCourseWeb ] Udemy - FPGA Embedded Design, Part 1 - Verilog
- CategoryOther
- TypeTutorials
- LanguageEnglish
- Total size394 MB
- Uploaded Byfreecoursewb
- Downloads53
- Last checkedJul. 16th '20
- Date uploadedJul. 14th '20
- Seeders 7
- Leechers3
[ FreeCourseWeb.com ] FPGA Embedded Design, Part 1 - Verilog
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Genre: eLearning | MP4 | Video: h264, 1280x720 | Audio: aac, 48000 Hz
Language: English | VTT | Size: 426 MB | Duration: 3.5 hours
What you'll learn
Design hardware behavior with the Verilog Hardware Description Language
Simulate Verilog Modules.
The FPGA Embedded Design curriculum will take you by the hand through learning Verilog, how to simulate your designs, how to make them real in an FPGA, and finally how to design and use your own Soft Processor. This will take place in a series of courses. This first course is about the Verilog Hardware Description Language.
This is NOT a System Verilog course. However, learning Verilog is a starting point if you want to learn System Verilog (Similar
Requirements
Basic programming knowledge sometimes helps, but the case of no programming experience can be an advantage since you will learn something other than traditional sequential programming.
Although a refresher is provided in this course, some basic digital electronics knowledge always helps. Not necessarily advanced stuff, just the basics: Logic gates, maybe flip flops, counters, tristate buffers, etc.
Ultimately, an FPGA development board will come in handy to build and test your projects. We'll use it starting at the second course in the series.
Description
Do you feel you've learned enough about microcontrollers? Do you want to learn more embedded application design techniques? How about a technique that will allow you to design high-performance systems the way professional equipment designers do?
If you're still interested, this curriculum is for you. The FPGA Embedded Design series will teach you the exquisite art of FPGA design.
So what is an FPGA anyway?
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Files:
- [ FreeCourseWeb.com ] Udemy - FPGA Embedded Design, Part 1 - Verilog.zip (394.0 MB)
Code:
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